Author Archives: Pete Davy

Four shifts that could change how ASIC physical design teams reach closure The most important change may be less about a new tool and more about a new way of working: engineers describe the outcome, while increasingly capable systems help … Continue reading →

Continuing from part three: the backend had turned the corner, until setup pressure increased again close to tapeout. Close to tapeout, timing pressure changes engineering behaviour. Teams start accepting optimisations they’d normally leave alone earlier in the flow, and that’s … Continue reading →

Continuing from part two: skew behaviour had improved, but something underneath was still fighting convergence. Even after we’d stabilised skew behaviour, convergence still felt fragile. One of the engineers on my team kept saying, “We’re still compensating for something.” He … Continue reading →

Continuing from part one: the backend was destabilising long before the reports clearly showed it. The next morning, my team focused on one question: why was CTS improving the timing numbers while making the backend physically less stable at the … Continue reading →

Over the next few posts, I’m going to walk through a real CTS recovery from a 28nm tapeout programme we worked on recently. This was an actual backend convergence failure that came uncomfortably close to derailing tapeout. What made this … Continue reading →

There’s a tendency to focus on leading-edge nodes. It’s understandable, but most of the interesting innovation right now is happening elsewhere, and particularly at the system level: Advanced packaging Chiplets Photonics Compound semiconductors Where the UK fits in This is … Continue reading →

A simple reality has come up in a few recent conversations: power has overtaken compute as the limiting factor in AI systems. It’s especially true in edge AI, where the power envelope is fixed and there’s no give in it. … Continue reading →

Most teams I speak to believe they’re ready for tapeout. Very few actually are. Over the last few years I’ve sat in on a number of semiconductor programmes at the sharp end of the schedule. The teams saying “we’re good … Continue reading →

AI silicon isn’t compute-bound anymore. It’s memory-bound. In several recent conversations (including around @ChipStartUK / Silicon Catalyst UK), one point kept coming up: 𝗔𝗜 𝘀𝘆𝘀𝘁𝗲𝗺𝘀 𝗮𝗿𝗲 𝗻𝗼𝘄 𝗱𝗼𝗺𝗶𝗻𝗮𝘁𝗲𝗱 𝗯𝘆 𝗺𝗲𝗺𝗼𝗿𝘆; 𝗼𝗳𝘁𝗲𝗻 𝗺𝗼𝗿𝗲 𝘁𝗵𝗮𝗻 𝗵𝗮𝗹𝗳 𝘁𝗵𝗲 𝘀𝘆𝘀𝘁𝗲𝗺. Memory scaling has effectively stalled … Continue reading →

How to approach physical design resourcing without blowing your burn rate Early on every semiconductor company faces the same dilemma: Should we build an internal physical design team, partner with specialists or both? Tarun has seen the models up close. … Continue reading →

That was the challenge for a recent space application ASIC. When a client building hardware for orbit approached NextGen, the brief was clear: Deliver a full DDR4 subsystem implementation with perfect clock alignment, first time right. Space doesn’t forgive mistakes. … Continue reading →

And that’s exactly why NextGen exists For 15 years, Tarun worked as a physical design contractor for UK, European and American semiconductor companies. Different companies. Different process nodes. Same message from clients: “Are you free? We just need someone we … Continue reading →

Introducing a new series of posts for the UK & EU semiconductor community: Inside Physical Design — Real Stories. Real Challenges. Real Tapeouts Over the next few weeks, we’re sharing short, honest insights from 25+ years of RTL-to-GDSII experience — … Continue reading →

The semiconductor industry talks endlessly about AI accelerators, chiplets and advanced nodes. But there’s a quieter challenge that determines whether ambitious chip designs actually make it to silicon: finding competent physical design engineers you can trust. After 15 years as … Continue reading →