When a client building hardware for orbit approached NextGen, the brief was clear:
Deliver a full DDR4 subsystem implementation with perfect clock alignment, first time right.
Space doesn’t forgive mistakes.
Radiation. Mission lifetime. Zero re-spin tolerance.
Our scope:
🔹 Floorplanning DDR PHYs, IO pads, bumps + a dedicated PLL
🔹 Custom clock-tree adaptations to meet interface alignment
🔹 Repeated skew/jitter analysis with ECO cycles
🔹 Full P&R, STA, physical verification, antenna + DRC/LVS fixes
Standard flows weren’t enough.
We had to script, adapt and iterate clock structures to align each bytelane precisely.
In the end, timing closure passed with margin.
Whilst the tapeout was for the prototype, the client taped out— and that subsystem has successfully started its journey for space!
This is where experienced physical design teams prove their value:
not for routine flows,but for the timing-critical, high-complexity, no-fallback work.