Microelectronics UK 2026: from funding to silicon

Microelectronics UK returned to Excel London on 29 and 30 September with over 4,000 attendees and a confident mood. Investors are warming to hardware again and the new Semiconductor Catapult launched on day one. Four observations stood out from conversations on our stand.

Founders are asking about execution

Founders arrived with funding secured and a sharper question: how do we get this to silicon? As our CEO Tarun Khurana put it on the Startup Launchpad stage, differentiation attracts funding. Execution delivers silicon.

“The RTL is nearly done” is still the riskiest sentence

Several teams described their RTL as almost complete, yet had not started floorplanning or power analysis. Physical problems found late cost the most to fix. Tarun’s advice struck a chord: design forward, plan tape-out backwards.

Cost pressure is driving ASIC interest

Product directors came with a commercial brief: lower bill of materials cost, better security, stronger protection of IP, smaller boards and less power in high volume products. For them a custom ASIC is a strong and achievable business case.  And on a legacy or even mainstream node, silicon costs are affordable for even modest volumes.

Hiring cannot keep pace

Design centre managers repeated a common story. Experienced physical design engineers take months to recruit and tape-out dates will not wait. Many now pair in-house teams with specialist partners for specific phases such as sign-off or DFT.

Continuing the conversation

NextGen Chip Design takes designs from RTL to GDSII, with tape-out execution, sign-off closure, DFT and mixed-signal integration. If we met on our stand, thank you. If we missed you, Contact Us