From AI features to progressively autonomous flows
August 25, 2026
Four shifts that could change how ASIC physical design teams reach closure The most important change may be less about...
(4/4) CTS recovery case study: what stability taught us about late-stage convergence
Continuing from part three: the backend had turned the corner, until setup pressure increased again close to tapeout. Close to...
(3/4) CTS recovery case study: when CTS started fighting the floorplan
Continuing from part two: skew behaviour had improved, but something underneath was still fighting convergence. Even after we'd stabilised skew...
(2/4) CTS recovery case study: how over-optimised skew destabilised the entire backend
Continuing from part one: the backend was destabilising long before the reports clearly showed it. The next morning, my team...
(1/4) CTS recovery case study: when clean timing reports hid a failing backend
Over the next few posts, I'm going to walk through a real CTS recovery from a 28nm tapeout programme we...
Rethink and innovate: why system-level design is where AI hardware innovation lives now
There's a tendency to focus on leading-edge nodes. It's understandable, but most of the interesting innovation right now is happening...
Power is the constraint on AI systems
A simple reality has come up in a few recent conversations: power has overtaken compute as the limiting factor in...
Readiness: An Illusion?
Most teams I speak to believe they're ready for tapeout. Very few actually are. Over the last few years I've...
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AI silicon isnβt compute-bound anymore.Β Itβs memory-bound. In several recent conversations (including around @ChipStartUK / Silicon Catalyst UK), one point kept...
Startups often get this decision wrong the first time
How to approach physical design resourcing without blowing your burn rate Early on every semiconductor company faces the same dilemma:...
